Some analog-to-digital converters (ADC) have a successive approximation register (SAR) topology. These converters work by comparing an analog voltage signal to known fractions of the full-scale input voltage and then setting or clearing bits in the ADC's data register. Some SAR converters use a capacitive digital-to-analog converter (C-DAC) to successively compare bit combinations. For example, the first bit is based on a comparison of half the full-scale input voltage to the input voltage. In response to the first comparison, the second bit is based on a comparison of either one quarter or three quarters of the full-scale input voltage.
Charge kickback occurs when the comparator is released from a reset condition and it is about to make a decision as to whether the voltage at the inverting input or the non-inverting input is greater. Just after the comparator is released from reset and depending on the speed of the comparator, it kicks a large amount of charge into the top plates of the capacitors. Some capacitors are coupled to positive metal oxide semiconductors (PMOS), and other capacitors are coupled to negative metal oxide semiconductors (NMOS). The NMOS and PMOS devices have different impedances, which causes the capacitors to drain at different rates. The result is different voltages on the capacitors during voltage decay, which causes errors when the voltages on the capacitors are compared.